1. Field of the Invention
The present invention relates to an oversampling circuit, a serial communication apparatus using the oversampling circuit, and an oversampling method.
2. Description of the Related Art
Many high-speed interface standards are becoming commercially practical in order to satisfy large-capacity and high-speed data transmission. For most of them, a serial transmission scheme is adopted. In the serial transmission scheme, data is transmitted based on a predetermined frequency. A clock of the frequency is superimposed on data to be transmitted. A data receiving unit extracts the clock from the received signal, and restores received data based on the extracted clock signal. The circuit for performing the restoration operation is called a clock data recovery (to be referred to as CDR hereinafter) circuit, for example.
In a conventional CDR circuit, generally, a PLL (Phase Locked Loop) circuit is used, in which an oscillation clock of a VCO (Voltage Controlled Oscillator) in the PLL circuit is controlled such that the oscillation clock synchronizes with the phase of the received data, and the oscillation clock is extracted as a restored clock. Then, by latching the received data on the basis of the restored clock, the received data is restored accurately.
However, due to increase of the data rate, the oscillation frequency of the VCO also increases. As to a CDR circuit embedding such a VCO, there are disadvantages such as increase of chip size, increase of consumption current, and increase of cost. Also, wiring delay cannot be neglected due to speed-up. Since element arrangement and wiring delay largely depend on characteristics of devices to be used, it becomes necessary to redesign the layout in each process, so that re-usability of the circuits is lowered and the development period increases.
For solving the problems, an oversampling type CDR circuit is proposed (refer to Japanese Laid-Open Patent Application No. 2005-192192 (patent document 1), for example). The oversampling type CDR circuit generates multiphase clocks in which phases are shifted at equal intervals based on a reference clock, so that input data is sampled by each phase to obtain oversampling data. The oversampling type CDR circuit detects timing at which the logic is reversed from the bit sequence of the oversampling data, and restores the clock and the data based on the result. By adopting such a configuration, since the circuit other than the multiphase clock generation unit can be configured by using a digital circuit, the circuit can be realized relatively easily.
As related techniques, there are techniques disclosed in Japanese Laid-Open Patent Application No. 2010-016545 (patent document 2) and Japanese Laid-Open Patent Application No. 2009-219021 (patent document 3).
The patent document 2 discloses an oversampling method using a multiphase clock generation circuit in order to perform oversampling while suppressing consumption current. The multiphase clock generation circuit includes plural delay lines. Each delay line is formed by delay elements that are serially connected for generating delay amount according to a bias voltage. The multiphase clock generation circuit also includes two bias voltages to be supplied to the delay elements of each delay line. The bias voltage is controlled such that the difference of signal passing times between delay lines becomes a desired value, so that multiphase clocks having desired phase differences are generated by supplying a reference clock to the delay lines.
The patent document 3 discloses a data recovery circuit for restoring serial data, that is serially transferred, by oversampling the data in order to suppress consumption current. The data recovery circuit includes a multiphase clock generation unit for generating multiphase clocks, a multiphase clock control unit for stopping a part of clocks of the multiphase clocks, an oversampling unit for oversampling serial data based on clocks that are not stopped by the multiphase clock control unit, and a symbol data restoring unit for restoring serial data based on the sampling data sampled by the oversampling unit.
In the data recovery circuit, since clocks are stopped from being supplied to latch circuits that latch each bit of oversampling data for which data recovery is not required. Thus, consumption current can be reduced compared to a conventional data recovery circuit.
However, in the invention described in the patent document 1, in the normal oversampling type CDR circuit, the multiphase clocks are generated by using DLL (Delay Locked Loop) in general. When the phase difference of the multiphase clocks requested from the system becomes very small, it becomes necessary to increase operation speed of delay elements of the DLL, so that there is a problem in that consumption current increases.
Also, since there is a limitation of operation speed of the delay elements of DLL, there may be a case in which phase difference of multiphase clock requested by the system cannot be realized.
On the other hand, in recent years, there is a communication standard for performing operation at plural data communication rates, and it is required to operate at plural data rates. Since 1 unit interval (UI) that is one bit cycle of serial data is determined by the data rate, the size of the 1 UI changes according to switching of data rates. The oversampling type CDR circuit performs sampling by dividing 1 UI into N (N is an integer equal to or greater than 1) (oversampling of N times). Thus, the oversampling interval changes when 1 UI changes.
For example, in PCl/express that is one of a high-speed serial communication standard, 3 types of data rates are standardized. The 3 types of data rates are 2.5 Gbps, 5 Gbps and 8 Gbps respectively, and 1 UI for the 3 types are 400 ps, 200 ps and 125 ps respectively. For example, when oversampling of 8 times is performed on the serial data, the oversampling intervals are 50 ps, 25 ps and 15.625 ps respectively, which means that the maximum value of the oversampling interval becomes greater than three times as large as the minimum value.
In a normal oversampling type CDR circuit, the timing clock for performing oversampling is generated by PLL or DLL.
Generally, since variation of delay amount in delay elements forming the PLL and the DLL is small, it is difficult to change the oversampling interval by changing the phase difference of the timing clocks in PLL and DLL. Therefore, in the invention described in the patent document 2, plural PLLs and DLLs are prepared for changing the oversampling intervals. Although each of PLL and DLL can generate a predetermined phase difference, there is a problem in that consumed power and the circuit area are increased.
In the invention described in patent document 2, since the number of delay elements forming each delay line and the number of delay lines are large, it cannot be expected to remarkably reduce consumption current compared to the oversampling circuit using the multiphase clocks generated by the normal DLL.
According to the invention described in the patent document 3, although consumption current is reduced compared to a normal circuit, the reduction of consumption current is not sufficient, and switching between data rates is not considered.